Next Gen Vending
Intel is seeking to integrate the Internet of Things (IoT) with the next generation of vending. The new solution integrates pre-validated building blocks that facilitate the integration of multiple compute workloads.
Cypress Controllers Allow Ezetap to Deliver Integrated mPOS
Cypress Semiconductor announced Ezetap mPOS solutions is using Cypress’s “CapSense Express” controllers in the world’s first capacitive-touch-based PIN-pad in its new MPOS device. The CY8CMBR2016 matrix keypad solution provides the Ezetap MPOS device with a durable user interface, helping it to pass all of the stringent EMVCo and PCI global certifications required for PIN entry devices. Consumer electronics and home appliances have rapidly been transitioning from mechanical buttons to capacitive touch controls. The EMV and PCI certifications are extremely strict due to the need to protect customer PINs against a broad range of attacks, while ensuring compatibility across a range of payment cards. Ezetap was able to go from concept, to certification, to manufacturing in less than a year.
Cypress Reports 4Q/FY/10 Results
Cypress Semiconductors posted 4Q/10 revenue of $226.6 million, down 2.3% from $231.9 million for the prior quarter, and up 16.8% from $194.0 million for the year-ago period. Meanwhile, net income for the quarter totaled $50.6 million. For the 2010 fiscal year, Cypress revenue totaled $883.8 million, an increase of 32.3% from fiscal year 2009 revenue of $667.8 million. Cypress’s fourth-quarter revenue decreased 2% sequentially thanks to its CCD division which grew 10% sequentially due to very strong “TrueTouch” touchscreen revenues, which drove the overall mobile handset revenues up 27%. Meanwhile FY 2010 revenue grew 32% year-over-year, rebounding strongly from a tough 2009 thanks to the Company’s “PSoC” and “TrueTouch” products having achieved record revenue and design wins.
MoSys to Present at the 47th Design Automation Conference
MoSys differentiated, high-density memory and high-speed interface (I/O) IP is participating at the 47th Annual Design Automation Conference, DAC 2010.
DAC is the worldâs leading technical conference and tradeshow, covering the latest trends in electronic design and design automation. MoSysâ Vice President
of Business Operations, is presenting âMoSys and TSMC Collaborating for Innovationâ in TSMCâs Open Innovation Platform Partner Theater on June 14, June 15
and June 16. The Director of Marketing at MoSys, is giving three presentations on June 14, June 15 and June 16. MoSys develops serial chip-to-chip
communications solutions for next generation networking systems and advanced system-on-chip (SoC) designs.
Cypress Launches 32-Mbit and 64-Mbit Asynchronous SRAMs
Cypress Semiconductor has Launched its 32-Mbit and 64-Mbit fast asynchronous SRAMs, providing very fast response times and the smallest footprint at these densities. The “CY7C1071DV33” 32-Mbit 3V and “CY7C1081DV33” 64-Mbit 3V fast asynchronous SRAMs offer both 16-bit and 8-bit I/O configuration. The new 32-Mbit and 64-Mbit SRAMs offer very fast access times of 12 ns. They are available in RoHS-compliant 48-BGA packages with a footprint of 8.0 x 9.5 x 1.2 mm and 8.0 x 9.5 x 1.4 mm, respectively. The new fast asynchronous SRAMs are fabricated using Cypress’ “90-nm C9” CMOS technology. Cypressâs broad portfolio of fast asynchronous and low-power SRAMs includes densities ranging from 4 Kbits to 64 Mbits in 90-nm process technology for POS terminals, gaming machines, storage, automotive and more.
Cypress Introduces Device Selection for Perfect PSoC Solution
Cypress Semiconductor has introduced its “Electronic Product Selector Guide” online product selection tool for its “PSoC 3” and “PSoC 5” architectures. Now available at www.cypress.com/go/PSoCePSG, the selection tool streamlines the selection of the optimal PSoC device based on the peripheral functions a designer wants to implement in the programmable analog and digital resources. As a user makes selections in the toolâs intuitive user interface, the âResultsâ field of applicable parts dynamically narrows down, displaying the part with the best match first. The “Electronic Product Selector Guide” allows designers to easily customize the number of ADCs, DACs, comparators, OpAmps, PGAs, TIAs and mixers needed in the analog subsystem; the number of timers, PWMs, counters and communications interfaces, including I2C, SPI, UART, I2S, Full-Speed USB and CAN, needed in the digital subsystem; and the speed, microcontroller core, memory, voltage, temperature range and package in the CPU subsystem.
G&D
Giesecke & Devrient (G&D) has developed the first prototype of a complete security platform for a mobile handset, with Qualcomm Incorporated’s support, and will be displaying its proof-of-concept solution running on Qualcomm’s Snapdragon chipsets at Mobile World Congress in Barcelona this week. The demo will show how the MobiCore(C) secure application environment and the Snapdragon’s security architecture delivers a complete ARM TrustZone technology-based security platform to address the requirements of services ranging from mobile payment with secure PIN entry and content management to key management and general user authentication. The MobiCore environment provides a fully certifiable security solution that enables applications using dedicated security solutions today to be integrated into advanced mobile devices based on Qualcomm’s Snapdragon platform. Additionally, G&D and Toro Development are working together to develop a cutting-edge offering for mobile financial applications based on G&D’s Mobile Security Card and TORO’s Akami mobile platform. Both companies are contributing their respective expertise in hardware, firmware, middleware, mobile software, and system architecture to create a platform offering system integrators, financial service providers, and retailers fast time to market for a proven secure mobile solution. This new offering brings to the market a series of stand-alone solutions for secure applications that will not necessarily evolve toward near-field communication (NFC), such as mobile banking, mobile remittance and mobile ATM. The Mobile Security Card originates from Giesecke & Devrient Secure Flash Solutions (G&D SFS), a joint venture between G&D and the flash controller supplier Phison Electronics.
G&D & ARM
Gieseck & Devrient have partnered with digital technology provider ARM
to offer secure mobile phone platforms. As a first step the two
companies will develop a joint prototype.Through the combination of ARM
TrustZone technology, which creates a protected
area in advanced systems-on-chip, and the highly secure Mobicore
operating system developed by G&D, sensitive applications such as
electronic payment and online banking via mobile phone will be
efficiently protected from security threats.
The interplay of TrustZone and Mobicore ensures that if online services
require security-sensitive functions such as entry of username and
password or data output on a display, these functions are transferred to
the Mobicore high-security operating system running in the TrustZone
protected area of an ARM application processor. As the
security-sensitive functions are executed, Mobicore maintains control of
the secure area of a system-on-chip. Users can therefore be certain that
the data they have entered, such as their username and password, cannot
be manipulated by malware on the phone during a payment transaction.
Acceptance of mobile applications such as banking, ticketing and payment
solutions rests on the security of device and background systems
involved. For this reason, both companies have been working on
innovative security concepts. The interplay of TrustZone and Mobicore
ensures that if online services
require security-sensitive functions such as entry of username and
password or data output on a display, these functions are transferred to
the Mobicore high-security operating system running in the TrustZone
protected area of an ARM application processor. As the
security-sensitive functions are executed, Mobicore maintains control of
the secure area of a system-on-chip. Users can therefore be certain that
the data they have entered, such as their username and password, cannot
be manipulated by malware on the phone during a payment transaction.
Cypress Semiconductor Architecture Inks Partnership
Cypress Semiconductor has teamed up with Keil tools division to deliver high-performance compiler options for the PSoC Creator IDE for the PSoC 3 and PSoC 5 programmable system-on-chip architectures. PSoC Creator enables engineers to design the way they think, using schematic-based design capture along with certified, pre-packaged peripherals to keep system creation independent of the target PSoC device. It includes free compilers from ARM; the Keil CA51 Compiler for PSoC 3 and the GNU GCC-ARM Compiler for PSoC 5, both bundled with the PSoC Creator distribution. Cypress delivers high-performance, mixed-signal, programmable solutions that provide customers with rapid time-to-market and exceptional system value with programmable system-on-chip families and derivatives such as PowerPSoC solutions for high-voltage and LED lighting applications, “CapSense” touch sensing, “TrueTouch” solutions for touchscreens and is the world leader in USB controllers.
MoSys & ROHM Enter into an Agreement to License 1T-SRAM
CA-based MoSys has entered into an agreement with electronic provider ROHM to license MoSysâ “1T-SRAM” embedded memory technology. The
technology license agreement will enable ROHM to design and manufacture ICs utilizing 1T-SRAM in ROHM’s fabrication facilities. Current and future generations of advanced SoCs (System-on-Chip) require significantly higher densities of embedded memory. MoSysâ patented 1T-SRAM IP, which has the advantage of enabling designs with 3 times the density in the same area as alternative solutions, high speed, low latency random access and superior reliability, provides a very
compelling solution for advanced SoC designs. MoSysâ patented 1T-SRAM® and 1T-Flash® memory technologies offer a combination of high density, low
power consumption, high speed and low cost advantages that are unmatched by other available memory technologies for a variety of networking,
computing, storage and consumer/graphics applications.
PANASONIC & RENESAS
Panasonic and Renesas Technology are set to concentrate their joint
development functions for SoC process technologies at the Renesas Naka
site and will start operation of their 28 to 32 nm process development
line installed at that site on October 1, 2009. Concentrating their
joint development functions at the Naka site with its 300 mm wafer line
and providing a joint development structure, the 2 companies are
developing 28 nm process technologies. They have agreed on joint
development of next-generation SoC technologies in 1998, before Renesas
was formed, and have continued to develop semiconductor process
technologies for the 90 nm, 65 nm, 45 nm, and 32 nm generations at the
Renesas Kitaitami site. In the development line at the Naka site, the
two companies have installed new production equipment in addition to
having transferred part of the development line equipment from the
Renesas Kitaitami site.
RENESAS WAVE
Renesas Technology and the city of Changchun, China have jointly carried
out a successful verification test of the world’s first commercial ITS
using public buses in the city throughout September. Renesas provided
the WAVE terminal platform that implements WAVE wireless communication
technology and confirmed the realization of WAVE communication used in
public buses. There are many efforts underway globally to implement ITS
that connect vehicles and the roads they drive on with a network to
resolve road and transportation problems such as traffic jams and road
accidents. Renesas developed the WAVE evaluation system in 2008 and has
participated in ITS verification testing at many locations.
Subsequently, according to Renesas, the WAVE technology will be able to
apply to safety monitoring of roads and public transportation systems.